In almost all forms of processing unit, e.g. central processing units or digital signal processors, instructions that control the operations of the system have a fixed size limit, often known as the instructions width. This limit imposes a restriction on how much each instruction can describe. In particular, processing systems which have multiple execution units or pipelines may be unable to usefully specify activity within all of those execution units or pipelines within the fixed width constraint of the instruction. This means that the full processing power of the system cannot always be fully utilized. One option would be to increase the width of the instructions size, for example by using very long instruction words. This, however, would slow down the instructions fetch and decoding process and would require wider parallel buses to transport the instructions.